Request for Cadence DML MacroModel Examples

The easiest way to develop MacroModels for Allegro PCB SI is to start with a well-documented working example of the type of model you need. It is much easier to edit an existing working model than create one from scratch.

Cadence has begun to develop DML MacroModel examples for some types of MGH drivers and receivers, and expects to add to these over time. Register now and you will be sent working examples of models with internal termination, driver pre-emphasis, receiver equalization and amplification, and other advanced effects.

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1) What is the maximum data rate for serial links on your current designs? *
< 2.5 Gbps 2 .5 Gbps 3.125 Gbps 3.125 to 6.25 Gbps > 6.25 Gbps

2) Do your serial drivers typically have pre-emphasis? *
no
Yes and modeled for SI analysis using HSPICE transistor level
Yes and modeled for SI analysis using IBIS
Yes and modeled for SI analysis using

3) What is the number of settings that can be programmed on your serial drivers? *
serial drivers are not programmable
Number of settings (please specify)

4) How many bits do you typically simulate to generate eye patterns? *
0 to 100
101 to 1000
1001 to 10000
10001 to 100000

5) What equalization do your receivers use? *
Active
Passive
Do not use equalization

This free webinar will provide additional information on Cadence DML MacroModeling.

Register now